Design For Test Technology

SoC testing is becoming more complicated as processes become more refined, circuit scale increases, circuit operation becomes faster, and much less power is consumed. To resolve this issue, in addition to compressed scan, memory BIST, and boundary scan DFT, we perform high quality testing using various types of DFT technology for improved test quality and yield.

[DFT Technologies Adopted by Socionext]

At-speed and low power test technologies for improved test quality

Test using on-chip PLL clocks

Test that controls power consumption during testing

Memory redundancy repair process and fault diagnosis technologies for improved yield